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fujitsu microelectronics data sheet copyright?2008 fujitsu microelectronics limited all rights reserved 2008.10 8-bit microcontroller cmos f 2 mc-8fx mb95200h/210h series mb95f204h/f204k/f203h /f203k/f202h/f202k mb95f214h/f214k/f213h /f213k/f212h/f212k description mb95200h/210h is a series of general-purpose, single-chi p microcontrollers. in addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. note: f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ?f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instructions ? bit manipulation instructions, etc. ? clock (main osc clock and sub-osc clock are only available in mb95f204h/f204k/f203h/f203k/f202h/ f202k ) ? selectable main clock source main osc clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) main internal cr clock (1/8/10 mhz 3%, maximum machine clock frequency: 10 mhz) ? selectable subclock source sub-osc clock (32.768 khz) external clock (32.768 khz) sub-internal cr clock (typ: 100 khz, min: 50 khz, max: 200 khz) ?timer ? 8/16-bit composite timer ? timebase timer ? watch prescaler ?lin-uart (mb95f204h/f204k/f203h/f203k/f202h/f202k) ? full duplex double buffer capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer (continued) ds07-12623-3e
mb95200h/210h series 2 ds07-12623-3e (continued) ? external interrupt ? interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low-power consumption (standby) modes ? 8/10-bit a/d converter ? 8-bit or 10-bit resolution can be selected. ? low power consumption (standby) mode ? stop mode ? sleep mode ?watch mode ? timebase timer mode ? i/o port (max: 17) (mb95f204k/f203k/f202k) ? general-purpose i/o ports (max): cmos i/o: 15, n-ch open drain: 2 ? i/o port (max: 16) (mb95f204h/f203h/f202h) ? general-purpose i/o ports (max): cmos i/o: 15, n-ch open drain: 1 ? i/o port (max: 5) (mb95f214k/f213k/f212k) ? general-purpose i/o ports (max): cmos i/o: 3, n-ch open drain: 2 ? i/o port (max: 4) (mb95f214h/f213h/f212h) ? general-purpose i/o ports (max): cmos i/o: 3, n-ch open drain: 1 ? on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) ? hardware/software watchdog timer ? built-in hardware watchdog timer ? low-voltage detection reset circuit ? built-in low-voltage detector ? clock supervisor counter ? built-in clock supervisor counter function ? programmable port input voltage level ? cmos input level / hysteresis input level ? flash memory security function ? protects the contents of flash memory
mb95200h/210h series ds07-12623-3e 3 product line-up (continued) part number parameter mb95 f204h mb95 f203h mb95 f202h mb95 f204k mb95 f203k mb95 f202k mb95 f214h mb95 f213h mb95 f212h mb95 f214k mb95 f213k mb95 f212k type flash memory product clock supervisor counter it supervises the main clock oscillation. rom capacity 16 kb 8 kb 4 kb 16 kb 8 kb 4 kb 16 kb 8 kb 4 kb 16 kb 8 kb 4 kb ram capacity 496 b 496 b 240 b 496 b 496 b 240 b 496 b 496 b 240 b 496 b 496 b 240 b low-voltage detection reset no yes no yes reset input dedicated software select dedicated software select cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (with machine clock = 16.25 mhz) interrupt processing time : 0.6 s (with machine clock = 16.25 mhz) general- purpose i/o i/o ports (max): 16 cmos: 15, n-ch: 1 i/o ports (max): 17 cmos: 15, n-ch: 2 i/o ports (max): 4 cmos: 3, n-ch: 1 i/o ports (max): 5 cmos: 3, n-ch: 2 timebase timer interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 mhz) hardware/ software watchdog timer reset generation cycle main oscillation clock at 10 mhz : 105 ms (min) the sub-internal cr clock can be used as the source clock of the hardware watchdog. wild register it can be used to replace three bytes of data. lin-uart a wide range of communication speed can be selected by a dedicated reload timer. it has a full duplex double buffer. clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. the lin function can be used as a lin master or a lin slave. no lin-uart 8/10-bit a/d converter 6 ch. 2 ch. 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 ch. 1 ch. the timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel". it has built-in timer function, pwc function , pwm function and input capture function. count clock: it can be selected from internal clocks (seven types) and external clocks. it can output square wave. external interrupt 6 ch. 2 ch. interrupt by edge detection (rising edge, falling edge, or both edges can be selected.) it can be used to wake up the device from standby modes. on-chip debug 1-wire serial control it supports serial writing. (asynchronous mode)
mb95200h/210h series 4 ds07-12623-3e (continued) part number parameter mb95 f204h mb95 f203h mb95 f202h mb95 f204k mb95 f203k mb95 f202k mb95 f214h mb95 f213h mb95 f212h mb95 f214k mb95 f213k mb95 f212k watch prescaler eight different time intervals can be selected. flash memory it supports automatic programming, embedded algorithm, write/erase/erase-suspend/erase-resume commands. it has a flag indicating the completion of the operation of embedded algorithm. number of write/eras e cycles (min): 100000 data retention time: 20 years for write/erase, external vpp(+10 v) input is required. flash security feature for protec ting the contents of the flash standby mode sleep mode, stop mode, watch mode, timebase timer mode package sdip-24 sop-20 dip-8 sop-8
mb95200h/210h series ds07-12623-3e 5 packages and corre sponding products o: available x: unavailable part number package mb95 f204h mb95 f203h mb95 f202h mb95 f204k mb95 f203k mb95 f202k mb95 f214h mb95 f213h mb95 f212h mb95 f214k mb95 f213k mb95 f212k 24-pin plastic sdip ooooooxxxxxx 20-pin plastic sop ooooooxxxxxx 8-pin plastic dip x x x x x x o o o o o o 8-pin plastic sop x x x x x x o o o o o o
mb95200h/210h series 6 ds07-12623-3e differences among products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash erase/program. for details of current consumption, see ? electrical characteristics?. ? package for details of information on each package, see ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of the operating voltage, see ? electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and 1 serial-wire be connected to an evaluation tool. in addition, if the flash memory data has to be updated, the rstx/pf2 pin must also be connected to the same evaluation tool.
mb95200h/210h series ds07-12623-3e 7 pin assignment p12/ec0/dbg n.c. p07/int07 p06/int06/to01 p05/int05/an05/to00/hclk2 p04/int04/an04/sin/hclk1/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 n.c. p64/ec1 x0/pf0 n.c. x1/pf1 vss x1a/pg2 x0a/pg1 vcc c rstx/pf2 to10/p62 n.c. to11/p63 (top view) 24 pins (sdip24) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 p12/ec0/dbg p06/int06/to01 p05/an05/to00/hclk2 p04/int04/an04/hclk1/ec0 vss vcc c rstx/pf2 (top view) 8 pins 8 7 6 5 1 2 3 4 * the number of usable pins is 20. p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00/hclk2 p04/int04/an04/sin/hclk1/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc c rstx/pf2 to10/p62 to11/p63 (top view) 20 pins 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10
mb95200h/210h series 8 ds07-12623-3e pin description (mb95200h series) (continued) pin no. pin name i/o circuit type* function 1pf0/x0b general-purpose i/o port this pin is also used as the main clock input oscillation pin. 2pf1/x1b general-purpose i/o port this pin is also used as the main clock input/output oscillation pin. 3v ss ? power supply pin (gnd) 4 pg2/x1a c general-purpose i/o port this pin is also used as the subc lock input/output oscillation pin. 5 pg1/x0a c general-purpose i/o port this pin is also used as the subclock input oscillation pin. 6v cc ? power supply pin 7 c ? capacitor connection pin 8pf2/rstxa general-purpose i/o port this pin is also used as a reset pin. this pin is a dedicated reset pin in mb95f204h/f203h/f202h. 9p62/to10d general-purpose i/o port high-current port this pin is also used as the 8/16-bit composite timer ch. 1 output. 10 p63/to11 d general-purpose i/o port high-current port this pin is also used as the 8/16-bit composite timer ch. 1 output. 11 p64/ec1 d general-purpose i/o port this pin is also used as the 8/16-bit composite timer ch. 1 clock input. 12 p00/an00 e general-purpose i/o port this pin is also used as the a/d converter analog input. 13 p01/an01 e general-purpose i/o port this pin is also used as the a/d converter analog input. 14 p02/int02/an02/ sck e general-purpose i/o port this pin is also used as the external interrupt input. this pin is also used as the a/d converter analog input. this pin is also used as the lin-uart clock i/o. 15 p03/int03/an03/ sot e general-purpose i/o port this pin is also used as the external interrupt input. this pin is also used as the a/d converter analog input. this pin is also used as the lin-uart data output. 16 p04/int04/an04/ sin/hclk1/ec0 f general-purpose i/o port this pin is also used as the external interrupt input. this pin is also used as the a/d converter analog input. this pin is also used as the lin-uart data input. this pin is also used as the external clock input. this pin is also used as the 8/16-bit composite timer ch. 0 clock input.
mb95200h/210h series ds07-12623-3e 9 (continued) *: for the i/o circuit types, see " i/o circuit type". pin no. pin name i/o circuit type* function 17 p05/int05/an05/ to00/hclk2 e general-purpose i/o port high-current port this pin is also used as the external interrupt input. this pin is also used as the a/d converter analog input. this pin is also used as the 8/16-bit composite timer ch. 0 output. this pin is also used as the external clock input. 18 p06/int06/to01 g general-purpose i/o port high-current port this pin is also used as the external interrupt input. this pin is also used as the 8/16-bit composite timer ch. 0 output. 19 p07/int07 g general-purpose i/o port this pin is also used as the external interrupt input. 20 p12/ec0/dbg h general-purpose i/o port this pin is also used as the dbg input pin. this pin is also used as the 8/16-bit composite timer ch. 0 clock input.
mb95200h/210h series 10 ds07-12623-3e pin description (mb95210h series) *: for the i/o circuit types, see " i/o circuit type". pin no. pin name i/o circuit type* function 1v ss ? power supply pin (gnd) 2v cc ? power supply pin 3 c ? capacitor connection pin 4 rstx/pf2 a general-purpose i/o port this pin is also used as a reset pin. this pin is a dedicated reset pin in mb95f214h/f213h/f212h. 5 p04/int04/an04/ hclk1/ec0 e general-purpose i/o port this pin is also used as the external interrupt input. this pin is also used as the a/d converter analog input. this pin is also used as the external clock input. this pin is also used as the 8/16-bit composite timer ch. 0 clock input. 6 p05/an05/to00/ hclk2 e general-purpose i/o port high-current port this pin is also used as the a/d converter analog input. this pin is also used as the 8/16-bit composite timer ch. 0 output. this pin is also used as the external clock input. 7 p06/int06/to01 g general-purpose i/o port high-current port this pin is also used as the external interrupt input. this pin is also used as the 8/16-bit composite timer ch. 0 output. 8 p12/ec0/dbg h general-purpose i/o port this pin is also used as the dbg input pin. this pin is also used as the 8/16-bit composite timer ch. 0 clock input.
mb95200h/210h series ds07-12623-3e 11 i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 10 m ? cmos output ? hysteresis input ? pull-up control available n- c h reset output / di g ital outpu t reset input / h y steresis outpu t standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95200h/210h series 12 ds07-12623-3e (continued) type circuit remarks d ? cmos output ? hysteresis input e ? cmos output ? hysteresis input ? pull-up control available f ? cmos output ? hysteresis input ?cmos input ? pull-up control available g ? hysteresis input ? cmos output ? pull-up control available h ? n-ch open drain output ? hysteresis input n-ch p-ch digital output digital output standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output
mb95200h/210h series ds07-12623-3e 13 notes on device handling ? preventing latch-ups when using the device, ensure that the voltage applied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in ?1. absolute maximum ratings? of electrical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increase s significantly, which may cause a component to be thermally destroyed. ? stabilizing su pply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctu ates rapidly even though the fluctuation is within the guaranteed operating range of the v cc power supply voltage. as a rule of voltage stabilizatio n, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. always pull up or pull down an unused input pin through a resistor of at least 2 k . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused output pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, prev ent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 f between the v cc pin and the v ss pin at a location close to this device. ? dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level after power-on until the reset output is released. ? rstx pin connect the rstx pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the rstx pin and the v cc or v ss pin when designing the layout of the printed circuit board. the rstx/pf2 pin functions as the reset input/output pin after power-on. in addition, the reset output can be enabled by the rstoe bit of the sysc register, and the reset input function or the general purpose i/o function can be selected by the rsten bit of the sysc register.
mb95200h/210h series 14 ds07-12623-3e ? c pin use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c c s dbg r s tx ? dbg/rstx/c pin connection diagram
mb95200h/210h series ds07-12623-3e 15 block diagram (mb95200h series) fla s h with s ecurity function (16/ 8 /4 kb) ram (496/240 b) interrupt controller 8 /10-bit a/d converter 8 /16-bit compo s ite timer (0) re s et with lvd o s cillator circuit cr o s cillator clock control on-chip debu g wild re g i s ter external interrupt lin-uart port port f 2 mc- 8 fx cpu internal bu s (p05 *3 /to00) (p06 *3 /to01) p12 * 1 /ec0, (p04/ec0) 8 /16-bit compo s ite timer (1) (p62 3 /to10) (p6 3 *3 /to11) p64/ec1 (p00/an00-p05 *3 /an05) pf2 * 1 /r s tx * 2 pf1/x1 * 2 pf0/x0 * 2 pg2/x1a * 2 pg1/x0a * 2 (p04/hclk1) (p05 *3 /hclk2) (p12/dbg) p02/int02-p07/int07 (p02/ s ck) (p0 3 / s ot) (p04/ s in) c v cc v ss * 1: pf2 a nd p12 a re nch open dr a in pin s . * 2: s oftw a re option *3 : p05, p06, p62 a nd p6 3 a re high-c u rrent port s .
mb95200h/210h series 16 ds07-12623-3e block diagram (mb95210h series) fla s h with s ecurity function (16/ 8 /4 kb) ram (496/240 b) interrupt controller 8 /10-bit a/d converter 8 /16-bit compo s ite timer (0) re s et with lvd cr o s cillator clock control on-chip debu g wild re g i s ter external interrupt port port f 2 mc- 8 fx cpu internal bu s (p05 *3 /to00) (p06 *3 /to01) p12 * 1 /ec0, (p04/ec0) p05 *3 /an05, (p04/an04) (p04/hclk1) (p05 *3 /hclk2) (p12/dbg) p04/int04, p06 *3 /int06 c v cc v ss * 1: pf2 a nd p12 a re nch open dr a in pin s . * 2: s oftw a re option *3 : p05 a nd p06 a re high-c u rrent port s . pf2 * 1 /r s tx * 2
mb95200h/210h series ds07-12623-3e 17 cpu core ? memory space the memory space of the mb95200h/210h series is 64 kb in size, and consists of an i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. the memory maps of the mb95200h/210h series are shown below. ? memory maps i/o 0000 h 0080 h - 0090 h ram 496 b 0280 h register 0100 h 0200 h - extension i/o 0f80 h 1000 h - c000 h flash 16 kb ffff h i/o 0000 h 0080 h - 0090 h ram 496 b 0280 h register 0100 h 0200 h - extension i/o 0f80 h 1000 h - e000 h flash 8 kb i/o - ram 240 b register - extension i/o - flash 4 kb ffff h 0000 h 0080 h 0090 h 0100 h 0180 h 0f80 h 1000 h f000 h ffff h mb95f204h/f204k /f214h/f214k mb95f203h/f203k/ f213h/f213k mb95f202h/f202k / f212h/f212k
mb95200h/210h series 18 ds07-12623-3e i/o map (mb95200h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w xxxxxx11 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 ch. 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 ch. 1 r/w 00000000 b 003a h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b
mb95200h/210h series ds07-12623-3e 19 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h to 0071 h ? (disabled) ? ? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h to 0075 h ? (disabled) ? ? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b
mb95200h/210h series 20 ds07-12623-3e p (continued) address register abbreviation register name r/w initial value 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register ch. 0 r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 status control register 0 ch. 1 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 status control register 0 ch. 1 r/w 00000000 b 0f99 h t11dr 8/16-bit composite timer 11 data register ch. 1 r/w 00000000 b 0f9a h t10dr 8/16-bit composite timer 10 data register ch. 1 r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 timer mode control register ch. 1 r/w 00000000 b 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b
mb95200h/210h series ds07-12623-3e 21 (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an undefined value is returned. address register abbreviation register name r/w initial value 0fe6 h to 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w xx000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95200h/210h series 22 ds07-12623-3e i/o map (mb95210h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w xxxxxx11 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h ? (disabled) ? ? 0017 h ? (disabled) ? ? 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h ? (disabled) ? ? 002b h ? (disabled) ? ? 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h ? (disabled) ? ? 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h ? (disabled) ? ? 0039 h ? (disabled) ? ? 003a h to 0048 h ? (disabled) ? ? 0049 h ? (disabled) ? ?
mb95200h/210h series ds07-12623-3e 23 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit control register ch. 4 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h ? (disabled) ? ? 0051 h ? (disabled) ? ? 0052 h ? (disabled) ? ? 0053 h ? (disabled) ? ? 0054 h ? (disabled) ? ? 0055 h ? (disabled) ? ? 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h to 0071 h ? (disabled) ? ? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h to 0075 h ? (disabled) ? ? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ? (disabled) ? ? 007c h ? (disabled) ? ? 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b
mb95200h/210h series 24 ds07-12623-3e (continued) address register abbreviation register name r/w initial value 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register ch. 0 r/w 00000000 b 0f97 h ? (disabled) ? ? 0f98 h ? (disabled) ? ? 0f99 h ? (disabled) ? ? 0f9a h ? (disabled) ? ? 0f9b h ? (disabled) ? ? 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h ? (disabled) ? ? 0fbd h ? (disabled) ? ? 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b 0fe6 h to 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configuration register r/w 11000011 b
mb95200h/210h series ds07-12623-3e 25 (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an undefined value is returned. address register abbreviation register name r/w initial value 0fe9 h cmcr clock monitoring control register r/w xx000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95200h/210h series 26 ds07-12623-3e interrupt source tabl e (mb95200h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sourc- es of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq0 fffa h fffb h l00 [1:0] high external interrupt ch. 5 irq1 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq2 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq3 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq4 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq5 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq6 ffee h ffef h l06 [1:0] lin-uart (reception) irq7 ffec h ffed h l07 [1:0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1:0] ? irq9 ffe8 h ffe9 h l09 [1:0] ? irq10 ffe6 h ffe7 h l10 [1:0] ? irq11 ffe4 h ffe5 h l11 [1:0] ? irq12 ffe2 h ffe3 h l12 [1:0] ? irq13 ffe0 h ffe1 h l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ?irq17ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] timebase timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ?irq21ffd0 h ffd1 h l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95200h/210h series ds07-12623-3e 27 interrupt source tabl e (mb95210h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sourc- es of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq0 fffa h fffb h l00 [1:0] high ? irq1 fff8 h fff9 h l01 [1:0] ? irq2 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 ? irq3 fff4 h fff5 h l03 [1:0] ? ? irq4 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq5 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq6 ffee h ffef h l06 [1:0] ?irq7ffec h ffed h l07 [1:0] ? irq8 ffea h ffeb h l08 [1:0] ? irq9 ffe8 h ffe9 h l09 [1:0] ? irq10 ffe6 h ffe7 h l10 [1:0] ? irq11 ffe4 h ffe5 h l11 [1:0] ? irq12 ffe2 h ffe3 h l12 [1:0] ? irq13 ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ?irq17ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] timebase timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ?irq21ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95200h/210h series 28 ds07-12623-3e electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6v input voltage* 1 v i v ss ? 0.3 v ss + 6v *2 output voltage* 1 v o v ss ? 0.3 v ss + 6v *2 maximum clamp current i clamp -2 +2 ma applicable to pins listed in *3 total maximum clamp current |i clamp | ? 20 ma applicable to pins listed in *3 ?l? level maximum output current i ol1 ? 15 ma other than p05, p06, p62 and p63 *4 i ol2 15 p05, p06, p62 and p63 *4 ?l? level average current i olav1 ? 4 ma other than p05, p06, p62 and p63 *4 average output current = operating current operating ratio (1 pin) i olav2 12 p05, p06, p62 and p63 *4 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ?100ma ?l? level total average output current i olav ?50ma total average output current = operating current operating ratio (total number of pins) ?h? level maximum output current i oh1 ? -15 ma other than p05, p06, p62 and p63 *4 i oh2 -15 p05, p06, p62 and p63 *4 ?h? level average current i ohav1 ? -4 ma other than p05, p06, p62 and p63 *4 average output current = operating current operating ratio (1 pin) i ohav2 -8 p05, p06, p62 and p63 *4 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ?-100ma ?h? level total average output current i ohav ?-50ma total average output current = operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a -40 +85 c storage temperature tstg -55 +150 c
mb95200h/210h series ds07-12623-3e 29 *1: the parameter is based on v ss = 0.0 v. *2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: applicable to the following pins: p00 to p07, p62 to p64, pg1, pg2, pf0, pf1 (p00 to p03, p07, p62 to p64, pg1, pg2, pf0 and pf1 are available in mb95f204h/f203h/f202h/f204k/f203k/f202k.) ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the hv (high voltage) signal is input is below the standard value, irrespective of whether the current is transient current of stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microc ontroller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: *4: p62 and p63 are available in mb95f204h/f203h/f202h/f204k/f203k/f202k. warning: a semiconductor device may be damaged by apply ing stress (voltage, current, temperature, etc.) in excess of the absolute maximum rating. therefore, ensure that not a single parameter exceeds its absolute maximum rating. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
mb95200h/210h series 30 ds07-12623-3e 2. recommended operating conditions (v ss =0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: the value is 2.88 v when the low-voltage detection reset is used. *3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the electrical characteristics of the device are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 * 2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f *3 operating temperature t a -40 +85 c other than on-chip debug function +5 +35 on-chip debug function dbg / r s tx / c pin connection dia g ram c c s r s tx dbg * s ince the dbg pin b ecome s a comm u nic a tion pin in on-chip de bu g mode, s et a p u ll- u p re s i s tor v a l u e su iting the inp u t/o u tp u t s pecific a tion s of p12/dbg. * :
mb95200h/210h series ds07-12623-3e 31 3. dc characteristics (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max "h" level input voltage v ihi p04 * 1 0.7 v cc ?v cc + 0.3 v when cmos input level (hysteresis input) is selected v ihs p00 to p07, p12, p62 to p64, pf0 to pf1, pg1 to pg2 * 1 0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v il p04 * 1 v ss ? 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p00 to p07, p12, p62 to p64, pf0 to pf1, pg1 to pg2 * 1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d pf2, p12 ? v ss ? 0.3 ? 0.2 v cc v ?h? level output voltage v oh1 output pins other than p05, p06, p62, p63, pf2 and p12 *2 i oh = -4 ma v cc ? 0.5 ? ? v v oh2 p05, p06, p62, p63 *2 i oh = -8 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p05, p06, p62 and p63 *2 i ol = 4 ma ? ? 0.4 v v ol2 p05, p06, p62, p63 *2 i ol = 2 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc -5 ? +5 a when pull-up resistance is disabled pull-up resistance r pull p00 to p07, pg1, pg2 *3 v i = 0 v 25 50 100 k when pull-up resistance is enabled
mb95200h/210h series 32 ds07-12623-3e (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf power supply current* 4 i cc v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?13 17 ma flash memory product (except writing and erasing) ? 33.5 39.5 ma flash memory product (at writing and erasing) ? 15 21 ma at a/d conversion i ccs v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?5.5 9 ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = + 25 c ? 65 153 a i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = +25 c ?10 84 a i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = +25 c ? 5 30 a
mb95200h/210h series ds07-12623-3e 33 (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: the input level of p04 can be switched between ?cmos input level? and ?hysteresis input level?. the input level selection register (ilsr) is used to switch between the two input levels. *2: p62 and p63 are available in mb95f204h/f203h/f202h/f204k/f203k/f202k. *3: p00 to p03, p07, pg1 and pg2 are available in mb95f204h/f203h/f202h/f204k/f203k/f202k. (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* 4 i ccmcr v cc v cc = 5.5 v f crh = 10 mhz f mp = 10 mhz main cr clock mode ?8.6?ma i ccscr v cc = 5.5 v sub-cr clock mode (divided by 2) t a = +25 c ?110410a i ccts v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz timebase timer mode t a = +25 c ?1.1 3ma i cch v cc = 5.5 v substop mode t a = +25 c ? 3.5 22.5 a main stop mode for single clock selection i lvd v cc current consumption for low-voltage detection circuit only ?3754a i crh current consumption for the internal main cr oscillator ?0.50.6ma i crl current consumption for the internal sub-cr oscillator oscillating at 100 khz ?2072a
mb95200h/210h series 34 ds07-12623-3e (continued) *4: ? the power supply current is determined by the external clock. when the low-voltage detection option is selected, the power- supply current will be the sum of adding th e current consumpti on of the low-voltage detection circuit (i lvd ) to a specified value. in addition, when both the low-voltage detection option and the internal cr oscillator are selected, the power supply current will be the sum of adding up the current con- sumption of the low-voltage detect ion circuit, the current consumption of the internal cr oscillators (i crh , i crl ) and a specified value. in on-chip debu g mode, the internal cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. ? see "4. ac characteristics: (1) clock timing" for f ch and f cl . ? see "4. ac characteristics: (2) source clock/machine clock" for f mp and f mpl .
mb95200h/210h series ds07-12623-3e 35 4. ac characteristics (1) clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0, hclk1, hclk2 x1 open 1 ? 12 mhz when the main external clock is used x0, x1, hclk1, hclk2 ? 1?32.5mhz f crh ?? 9.7 10 10.3 mhz when the main internal clock is used 3.3 v vcc 5.5 v(-40 c t a 40 c) 2.4 v vcc < 3.3 v(0 c t a 40 c) 7.76 8 8.24 mhz 0.97 1 1.03 mhz 9.55 10 10.45 mhz when the main internal clock is used 3.3 v vcc 5.5 v (40 c < t a 85 c) 7.64 8 8.36 mhz 0.955 1 1.045 mhz 9.5 10 10.5 mhz when the main internal clock is used 2.4 v vcc < 3.3 v (-40 c t a < 0 c, 40 c < t a 85 c) 7.6 8 8.4 mhz 0.95 1 1.05 mhz f cl x0a, x1a ? ? 32.768 ? khz when the main oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 200 khz when the sub-internal cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0, hclk1, hclk2 x1 open 83.4 ? 1000 ns when the external clock is used x0, x1, hclk1, hclk2 ? 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used
mb95200h/210h series 36 ds07-12623-3e (continued) (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max input clock pulse width t wh1 t wl1 x0, hclk1, hclk2 x1 open 33.4 ? ? ns when the external clock is used, the duty ratio should range between 40% and 60%. x0, x1, hclk1, hclk2 ?12.4??ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0, hclk1, hclk2 x1 open ? ? 5 ns when the external clock is used x0, x1 hclk1, hclk2 ???5ns internal cr oscillation start time t crhwk ????80s when the main internal cr clock is used t crlwk ????10s when the sub-internal cr clock is used
mb95200h/210h series ds07-12623-3e 37 x0, x1, hclk1, hclk2 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf figure of main clock input port external connection when a crystal oscillator or a ceramic oscillator is used when the external clock is used x0 x1 x0 x1 f ch f ch when the external clock is used (x1 is open) x0 x1 open f ch x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf figure of subclock input port external connection when a crystal oscillator or a ceramic oscillator is used when the external clock is used x0a x1a x0a x1a open f cl f cl
mb95200h/210h series 38 ds07-12623-3e (2) source clock/machine clock (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: this is the clock before it is divided according to the divi sion ratio set by the machine clock division ratio selection bits (sycc : div1 and div0) . this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio selection bits (sycc : div1 and div0) . in addition, a source clock can be selected from the following. ? main clock divided by 2 ? main cr clock ? subclock divided by 2 ? sub-cr clock divided by 2 (continued) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 (clock before division) t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 100 ? 1000 ns when the main cr clock is used min: f crh = 10 mhz max: f crh = 1 mhz ?61?s when the sub-oscilla tion clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-oscilla tion clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used 1 ? 10 mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 100 ? 16000 ns when the main cr clock is used min: f sp = 10 mhz max: f sp = 1 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.0625 ? 10 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the su b-oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95200h/210h series ds07-12623-3e 39 (continued) *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16
mb95200h/210h series 40 ds07-12623-3e schematic diagram of the clock generation block f ch (main oscillation) f crh (internal main cr clock) f cl (sub-oscillation) f crl (internal sub- cr clock) sclk (source clock) mclk (machine clock) clock mode select bits (sycc2: rcs1, rcs0) division circuit x x x x 1 1/4 1/8 1/16 divided by 2 divided by 2 divided by 2 operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp ) operating voltage - operating frequency (when t a = -40 o c to +85 o c) mb95200h/210h (without the on-chip debug function) operating voltage - operating frequency (when t a = +5 o c to +35 o c) mb95200h/210h (with the on-chip debug function)
mb95200h/210h series ds07-12623-3e 41 (3) external reset (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: see ?(2) source clock/machine clock? for t mclk . *2: the oscillation time of an oscilla tor is the time that th e amplitude reaches 90%. t he crystal oscillator has an oscillation time of between se veral ms and tens of ms. the ceramic os cillator has an oscillati on time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr oscillator clock has an oscillation time of betwee n several s and several ms. parameter symbol value unit remarks min max rstx ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator* 2 + 100 ?s in stop mode, subclock mode, sub-sleep mode, and watch mode 100 ? s in timebase timer mode 0.2 v cc rstx 0.2 v cc t rstl 0.2 v cc 0.2 v cc 100 s rstx x0 internal operating clock 90% of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction internal reset in normal operation in stop mode, sub-clock mode, sub-sleep mode, watch mode, and power-on t rstl
mb95200h/210h series 42 ds07-12623-3e (4) power-on reset (v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode limiting the slope of rising within 30 mv/ms is recommended. a sudden change of power supply voltage may activate the power- on reset function. when changing the power supply voltage during the operation, set the slope of rising to within 30 mv/ms as shown below. note:
mb95200h/210h series ds07-12623-3e 43 (5) peripheral input timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: see ?(2) source clock/machine clock? for t mclk . *2: int02, int03, int05, int07 and ec1 are available in mb95f204h/f203h/f202h/f204k/f203k/f202k. parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07, ec0, ec1 *2 2 t mclk *1 ?ns peripheral input ?l? pulse width t ihil 2 t mclk *1 ?ns int02 to int07, ec0, ec1 *2 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95200h/210h series 44 ds07-12623-3e (6) lin-uart timing (available in mb95f204h/f203h/f202h/f204k/f203k/f202k only) sampling is executed at the rising edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot -95 +95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95200h/210h series ds07-12623-3e 45 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc internal shift clock mode sck sot sin t slove t ivshe t shixe 2.4 v 0.8 v t f t r t slsh t shsl 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc external shift clock mode
mb95200h/210h series 46 ds07-12623-3e sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to de lay the output signal of the serial clock for half the clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot -95 +95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ?ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95200h/210h series ds07-12623-3e 47 2.4 v 2.4 v 0.8 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc internal shift clock mode sck sot sin t shove t ivsle t slixe 2.4 v 0.8 v t f t r t shsl t slsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc external shift clock mode
mb95200h/210h series 48 ds07-12623-3e sampling is executed at the rising edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that de lays the output signal of the serial clock for half clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot -95 +95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns 2.4 v 0.8 v 0.8 v t shovi t sovli t ivsli t slixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95200h/210h series ds07-12623-3e 49 sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1:there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that de lays the output signal of the serial clock for half clock. *3: see ? (2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock opera- tion output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot -95 +95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns 0.8 v 2.4 v 2.4 v t slovi t sovhi t ivshi t shixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95200h/210h series 50 ds07-12623-3e (7) low-voltage detection (v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max release voltage v dl + 2.52 2.7 2.88 v at power supply rise detection voltage v dl ? 2.42 2.6 2.78 v at power supply fall hysteresis width v hys 70 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 1??s slope of power supply that the reset release signal generates ? 3000 ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 300 ? ? s slope of power supply that the reset detection signal generates ?300?s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??300s reset detection delay time t d2 ??20s
mb95200h/210h series ds07-12623-3e 51 v hys t d2 t d1 t r t f v cc internal reset signal v on v off v dl+ v dl- time time
mb95200h/210h series 52 ds07-12623-3e 5. a/d converter (1) a/d converter electr ical characteristics (v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ? ? 10 bit total error - 3? + 3lsb linearity error - 2.5 ? + 2.5 lsb differential linear error - 1.9 ? + 1.9 lsb zero transition voltage v ot v ss ? 1.5 lsb v ss + 0.5 lsb v ss + 2.5 lsb v full-scale transition voltage v fst v cc ? 4.5 lsb v cc ? 2 lsb v cc + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v v cc 5.5 v 1.8 ? 16500 s 4.0 v v cc < 4.5 v sampling time ? 0.6 ? s 4.5 v v cc 5.5 v, with external impedance < 5.4 k 1.2 ? s 4.0 v v cc 4.5 v, with external impedance < 2.4 k analog input current i ain -0.3 ? + 0.3 a analog input voltage v ain v ss ?v cc v
mb95200h/210h series ds07-12623-3e 53 (2) notes on using the a/d converter ? external impedance of analog input and its sampling time ? the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to sati sfy the a/d conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. ? a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. comparator analog input during sampling: on note: the values are reference values. ~ ~ ~ ~ < = < = 4.5 v v cc 5.5 v : r 1.95 k (max), c 17 pf (max) ~ ~ ~ ~ < = < 4.0 v v cc 4.5 v : r 8.98 k (max), c 17 pf (max) r c ? analog input equivalent circuit [external impedance = 0 k to 100 k ] external impedance [k ] external impedance [k ] minimum sampling time [ s] minimum sampling time [ s] [external impedance = 0 k to 20 k ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 024681012 14 1 023 4 (v cc > = 4.5 v) (v cc > = 4.0 v) (v cc > = 4.5 v) (v cc > = 4.0 v) ? relationship between external impedance and minimum sampling time
mb95200h/210h series 54 ds07-12623-3e (3) definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ?11 1111 1110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a theoretical value. the error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v ss v fst ideal i/o characteristics v cc 001 002 003 004 3fd 3fe 3ff digital output digital output 2.0 lsb v ot 1 lsb 0.5 lsb total error analog input analog input 001 002 003 004 3fd 3fe 3ff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) to n {1 lsb x (n-1) + 0.5 lsb} v nt v ss v cc total error of digital output n v nt - {1 lsb x (n - 1) + 0.5 lsb} 1 lsb [lsb] = v cc - v ss 1024 (v) 1 lsb =
mb95200h/210h series ds07-12623-3e 55 (continued) zero transition error linearity error full-scale transition error 001 002 003 004 3fd 3fe 3ff digital output differential linear error of digital output n v (n+1)t - v nt 1 lsb - 1 = linearity error of digital output n v nt - {1 lsb x n + v ot } 1 lsb = digital output analog input 001 002 3fc 3fd 003 3fe 3ff 004 actual conversion characteristic ideal characteristic actual conversion characteristic v ot (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc analog input v ss v cc digital output analog input v ss v cc ideal characteristic {1 lsb x n + v ot } actual conversion characteristic ideal characteristic actual conversion characteristic v ot (measurement value) v fst (measurement value) v nt differential linearity error n-2 n-1 n n+1 digital output analog input v ss v cc actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n+1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) to n v ot (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc - 2.0 lsb [v]
mb95200h/210h series 56 ds07-12623-3e 6. flash memory program/erase characteristics *1: t a = +25 c, v cc = 5.0 v, 100000 cycles *2: t a = +85 c, v cc = 4.5 v, 100000 cycles *3: this value is converted fr om the result of a te chnology reliability assessment. (t he value is converted from the result of a high temperature accelerated test by using the arrhenius equation with the average temperature being +85 c) . parameter value unit remarks min typ max chip erase time ? 1* 1 15* 2 s 00 h programming time prior to erasure is excluded. byte programming time ? 32 3600 s system-level overhead is excluded. erase/program voltage 9.5 10 10.5 v the erase/program voltage must be applied to the rstx pin in erase/program. erase/program cycle ? 100000 ? cycle power supply voltage at erase/ program 4.5 ? 5.5 v flash memory data retention time 20* 3 ? ? year average t a = +85 c
mb95200h/210h series ds07-12623-3e 57 sample electrical characteristics ? power supply current ? temperature (continued) i cc - v cc t a =+25c, f mp =2, 4, 8 , 10, 16 mhz (divided b y 2) m a in clock mode with the extern a l clock oper a ting v cc [v] i cc [ma] f mp =16 mhz f mp =10 mhz f mp = 8 mhz f mp =4 mhz f mp =2 mhz 2 3 4567 20 15 10 5 0 i cc - t a v cc =5.5 v, f mp =10, 16 mhz (divided b y 2) m a in clock mode with the extern a l clock oper a ting t a [c] i cc [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =16 mhz f mp =10 mhz i cc s - v cc t a =+25c, f mp =2, 4, 8 , 10, 16 mhz (divided b y 2) m a in s leep mode with the extern a l clock oper a ting v cc [v] i cc s [ma] f mp = 8 mhz f mp =10 mhz f mp =16 mhz f mp =4 mhz f mp =2 mhz 2 3 4567 20 15 10 5 0 i cc s - t a v cc =5.5 v, f mp =10, 16 mhz (divided b y 2) m a in s leep mode with the extern a l clock oper a ting t a [c] i cc s [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =16 mhz f mp =10 mhz i ccl - v cc t a =+25c, f mpl =16 khz (divided b y 2) sub clock mode with the extern a l clock oper a ting v cc [v] i ccl [ a] 2 3 4567 100 75 50 25 0 i ccl - t a v cc =5.5 v, f mpl =16 khz (divided b y 2) sub clock mode with the extern a l clock oper a ting t a [c] i ccl [ a] -50 0 +50 +100 +150 100 75 50 25 0
mb95200h/210h series 58 ds07-12623-3e (continued) (continued) i ccl s - v cc t a =+25c, f mpl =16 khz (divided b y 2) subs leep mode with the extern a l clock oper a ting v cc [v] i ccl s [ a] 2 3 4567 100 75 50 25 0 i ccl s - t a v cc =5.5 v, f mpl =16 khz (divided b y 2) subs leep mode with the extern a l clock oper a ting t a [c] i ccl s [ a] -50 0 +50 +100 +150 100 75 50 25 0 i cct - v cc t a =+25c, f mpl =16 khz (divided b y 2) clock mode with the extern a l clock oper a ting v cc [v] i cct [ a] 2 3 4567 100 75 50 25 0 i cct - t a v=5.5 v, f mpl =16 khz (divided b y 2) clock mode with the extern a l clock oper a ting t a [c] i cct [ a] -50 0 +50 +100 +150 100 75 50 25 0 i ct s - v cc t a =+25c, f mp =2, 4, 8 , 10, 16 mhz (divided b y 2) time bas e timer mode with the extern a l clock oper a ting v cc [v] i ct s [ma] 2 3 4567 2.0 1.5 1.0 0.5 0.0 f mp =2 mhz f mp =4 mhz f mp = 8 mhz f mp =16 mhz f mp =10 mhz i ct s - t a v=5.5 v, f mp =10, 16 mhz (divided b y 2) time bas e timer mode with the extern a l clock oper a ting t a [c] i ct s [ma] -50 0 +50 +100 +150 2.0 1.5 1.0 0.5 0.0 f mp =10 mhz f mp =16 mhz
mb95200h/210h series ds07-12623-3e 59 (continued) i cch - v cc t a =+25c, f mpl =( s top) subs top mode wtih the extern a l clock s topping v cc [v] i cch [ a] 2 3 4567 20 15 10 5 0 i cch - t a v=5.5 v, f mpl =( s top) subs top mode with the extern a l clock s topping t a [c] i cch [ a] -50 0 +50 +100 +150 20 15 10 5 0 i ccmcr - v cc t a =+25c, f mp =1, 8 , 10 mhz (no divi s ion) m a in clock mode with the intern a l m a in cr clock oper a ting v cc [v] i ccmcr [ma] 2 3 4567 20 15 10 5 0 f mp = 8 mhz f mp =1 mhz f mp =10 mhz i ccmcr - t a v=5.5 v, f mpl =1, 8 , 10 mhz (no divi s ion) m a in clock mode with the intern a l m a in cr clock oper a ting t a [c] i ccmcr [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =1 mhz f mp = 8 mhz f mp =10 mhz i cc s cr - v cc t a =+25c, f mpl =50 khz (divided b y 2) sub clock mode with the intern a l sub -cr clock oper a ting v cc [v] i cc s cr [ a] 2 3 4567 200 150 100 50 0 f mpl =50 khz i cc s cr - t a v cc =5.5 v, f mpl =50 khz (divided b y 2) sub clock mode with the intern a l sub -cr clock oper a ting t a [c] i cc s cr [ a] -50 0 +50 +100 +150 200 150 100 50 0 f mpl =50 khz
mb95200h/210h series 60 ds07-12623-3e ? input voltage v ihi - v cc a nd v ili - v cc t a =+25c v cc [v] v ihi /v ili [v] 2 3 4567 5 4 3 2 1 0 v ihi v ili v ih s - v cc a nd v il s - v cc t a =+25c v cc [v] v ih s /v il s [v] 2 3 4567 5 4 3 2 1 0 v il s v ih s v ihm - v cc a nd v ilm - v cc t a =+25c v cc [v] v ihm /v ilm [v] 2 3 4567 5 4 3 2 1 0 v ilm v ihm
mb95200h/210h series ds07-12623-3e 61 ? output voltage (v cc -v oh1 ) - i oh t a =+25c i oh [ma] v cc -v oh1 [v] v cc =2.4 v v cc =2.7 v v cc = 3 .5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v 0-2-4-6- 8 -10 1.0 0. 8 0.6 0.4 0.2 0.0 (v cc -v oh2 ) - i oh t a =+25c i oh [ma] v cc -v oh2 [v] 0-2-4-6- 8 -10 1.0 0. 8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc = 3 .5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v v ol1 - i ol t a =+25c i ol [ma] v ol1 [v] 0246 8 10 1.0 0. 8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc = 3 .5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v v ol2 - i ol t a =+25c i ol [ma] v ol2 [v] 02 4 6 8 10 12 1.0 0. 8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc = 3 .5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v
mb95200h/210h series 62 ds07-12623-3e ? pull-up r pull - v cc t a =+25c v cc [v] r pull [k ] 2 3 456 250 200 150 100 50 0
mb95200h/210h series ds07-12623-3e 63 mask options no. part number mb95f204h mb95f203h mb95f202h mb95f214h mb95f213h mb95f212h mb95f204k mb95f203k mb95f202k mb95f214k mb95f213k mb95f212k selection method setting disabled setting disabled 1 low-voltage detection reset ? with low-voltage detection reset ? without low-voltage detec- tion reset without low-voltage detection reset with low-voltage detection reset 2 reset ? with dedicated reset input ? without dedicated reset in- put with dedicated reset input without dedicated reset input
mb95200h/210h series 64 ds07-12623-3e ordering information part number package mb95f204hp-g-sh-sne2 mb95f204kp-g-sh-sne2 mb95f203hp-g-sh-sne2 mb95f203kp-g-sh-sne2 MB95F202HP-G-SH-SNE2 mb95f202kp-g-sh-sne2 24-pin plastic sdip (dip-24p-m07) mb95f204hpf-g-sne2 mb95f204kpf-g-sne2 mb95f203hpf-g-sne2 mb95f203kpf-g-sne2 mb95f202hpf-g-sne2 mb95f202kpf-g-sne2 20-pin plastic sop (fpt-20p-m09) mb95f214hph-g-sne2 mb95f214kph-g-sne2 mb95f213hph-g-sne2 mb95f213kph-g-sne2 mb95f212hph-g-sne2 mb95f212kph-g-sne2 8-pin plastic dip (dip-8p-m03) mb95f214hpf-g-sne2 mb95f214kpf-g-sne2 mb95f213hpf-g-sne2 mb95f213kpf-g-sne2 mb95f212hpf-g-sne2 mb95f212kpf-g-sne2 8-pin plastic sop (fpt-8p-m08)
mb95200h/210h series ds07-12623-3e 65 package dimensions please check the latest package di mensions at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 24-pin pl as tic dip le a d pitch 1.778 mm p a ck a ge width p a ck a ge length 6.40 mm 22.86 mm s e a ling method pl as tic mold mo u nting height 4.80 mm m a x 24-pin pl as tic dip (dip-24p-m07) (dip-24p-m07) c 2008 fujit s u microelectronic s limited d24066 s -c-1-1 #22.86 0.10(.900 .004) index typ. 7.62(. 3 00) 6.40 0.10 (.252 .004) btm e-mark ? 0.04 +.004 ? .002 .010 0.25 +0.10 1 12 24 1 3 4.80(.189)max +0.20 ? 0. 3 0 +.008 ? .012 3 .00 .118 1.778(.070) (.0 3 9 . 004) 1.00 0.10 +0.09 ? 0.04 +.004 ? .002 .017 0.4 3 min 0.50(.020) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 2) pin s width do not incl u de tie b a r c u tting rem a inder. note 3 )# : the s e dimen s ion s do not incl u de re s in protr us ion.
mb95200h/210h series 66 ds07-12623-3e (continued) please check the latest package di mensions at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 20-pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 7.50 mm 12.70 mm le a d s h a pe g u llwing le a d bend direction norm a l bend s e a ling method pl as tic mold mo u nting height 2.65 mm m a x 20-pin pl as tic s op (fpt-20p-m09) (fpt-20p-m09) c 2008 fujit s u microelectronic s limited f200 3 0 s -c-1-1 det a il s of "a" p a rt index 0.10(.004) (.008 .004) 0.20 0.10 ? .007 +.005 .099 ? 0.17 +0.1 3 2.52 (mo u nting height) 0~8 ( s t a nd off) 0.80 +0.47 ? 0. 3 0 .0 3 1 +.019 ? .012 "a" ? .001 +.00 3 .010 0.25 +0.07 ? 0.02 #12.70 0.10(.500 .004) 11 20 1.27(.050) 1 10 0.25(.010) m ? 0.05 +0.09 0.40 .016 +.004 ? .002 #7.50 0.10 (.295 .004) ? 0.20 +0.40 10.2 .402 +.016 ? .008 btm e-mark dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 2) pin s width do not incl u de tie b a r c u tting rem a inder. note 3 )# : the s e dimen s ion s do not incl u de re s in protr us ion.
mb95200h/210h series ds07-12623-3e 67 (continued) please check the latest package di mensions at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 8-pin pl as tic dip le a d pitch 2.54 mm s e a ling method pl as tic mold 8-pin pl as tic dip (dip-8p-m0 3 ) (dip-8p-m0 3 ) c 2006-2008 fujit s u microelectronic s limited d08008 s -c-1- 3 0.25 0.05 (.010 .002) 15 max . 3 70 ? .012 +.016 ? 0. 3 0 +0.40 9.40 (.250 .010) 6. 3 5 0.25 index 14 85 0.50(.020) min typ. 2.54(.100) (.018 .00 3 ) 0.46 0.08 3 .00(.118)min 4. 3 6(.172)max 1.52 .060 ? 0 +.012 ? 0 +0. 3 0 ? 0 ? 0 0.99 +0. 3 0 +.012 .0 3 9 .0 3 5 0.89 +.014 +0. 3 5 ?. 012 ? 0. 3 0 typ. 7.62(. 3 00) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s
mb95200h/210h series 6 8 ds07-12623-3e (continued) please check the latest package di mensions at the following url. http://edevice.fujitsu.com/package/en-search/ 8-pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 5. 3 0 mm 5.24 mm le a d s h a pe g u llwing le a d bend direction norm a l bend s e a ling method pl as tic mold mo u nting height 2.10 mm m a x 8-pin pl as tic s op (fpt-8p-m08) (fpt-8p-m08) c 2008 fujit s u microelectronic s limited f08016 s -c-1-1 det a il s of "a" p a rt #5. 3 0 0.10 (.209 .004) index 1.27(.050) 1 4 5 8 0.4 3 0.05 (.017 .002) "a" ( s t a nd off) 0~8 (mo u nting height) 2.10(.08 3 ) max 0.10 +0.15 ? 0.05 ? .002 +.006 .004 7.80 +0.45 ? 0.10 +.018 ? .004 . 3 07 #5.24 0.10 (.206 .004) btm e-mark 0.20 0.05 (.008 .002) +0.10 ? 0.20 0.75 .0 3 0 +.004 ? .008 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 2) pin s width do not incl u de tie b a r c u tting rem a inder. note 3 ) # : the s e dimen s ion s do not incl u de re s in protr us ion.
mb95200h/210h series ds07-12623-3e 69 major revisions in this edition page section revision details ? ? preliminary data sheet data sheet ? programming flash memory microcontrollers using serial programmer this section was deleted. 57 to 62 sample electrical characteristics this is a new section.
mb95200h/210h series 70 ds07-12623-3e memo
mb95200h/210h series ds07-12623-3e 71 memo
mb95200h/210h series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu. com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectroni cs pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further inform ation please cont act each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the de vice with respect to use based on such information. when you develop equipment incor porating the device based on such inform ation, you must assume any res ponsibility arising out of su ch use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringement of any th ird-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fa tal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead direct ly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight contro l, air traffic control, mass transport control, medical life support syst em, missile launch con trol in weapon system), or (2) for use requiring extrem ely high reliability (i.e., submersibl e repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited: business & media promotion dept.

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